About Us
Cadence
This page provides information only about the Cadence software used by Department of Computer Science and Engineering and Department of Electrical Engineering at University of South Florida. Cadence tools are used at the USF to teach CMOS VLSI required core class (CSE Dept.,) for Computer Engineering Students every year which has 60+ student enrollment. Cadence software is also used for VLSI Design and CAD (Digital/Analog IC and Verification). This page is maintained by the Department of Computer Science and Engineering at USF, and was last modified 06/05/2024.
Cadence design tools in our curriculum
Cadence software products (Custom IC, SiP, Digital IC, Verification, SPB) are being used primarily in the following classes and research:
Class: CMOS VLSI Design (CSE core course for CompE students)
Class: VLSI Design in Nano-scaled Technologies (CSE Elective)
Class: Low Power VLSI Design (CSE Elective)
Class: Analog CMOS VLSI Design (EE elective)
Class: System on a Chip (EE Elective)
Graduate Research: VLSI Design & CAD - Cadence products are utilized for High Performance, Low Power VLSI Synthesis at all levels( Behavioral, RTL, Gate-level, and Physical Design). System-on-a-Chip design, test, and applications. MRAM Circuit Design and Modeling. Robust circuits and Hardware Security. On-chip power management. Side-channel power analysis attack mitigation.
For more information on how Cadence products are utilized in the CSE department at USF you can contact Dr. Srinivas Katkoori.
Cadence is a registered trademark of Cadence Design Systems, Inc.,
2655 Seely Avenue, San Jose, CA 95134
This page is maintained by the Department of Computer Science and Engineering at USF, and was last modified on 06/05/2024.
Disclaimer: "Information Provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment."